In current complementary metal oxide semiconductor (CMOS) technology, a polysilicon gate is typically employed. One disadvantage of utilizing polysilicon gates is that at inversion the polysilicon gates generally experience depletion of carriers in the area of the polysilicon gate that is adjacent to the gate dielectric. This depletion of carriers is referred to in the art as the polysilicon depletion effect. The depletion effect reduces the effective gate capacitance of the CMOS device. Ideally, it is desirable that the gate capacitance of the CMOS device be high since high gate capacitance typically equates to more charge being accumulated in the inversion layer. As more charge is accumulated in the channel, the source/drain current becomes higher when the transistor is biased.
CMOS devices including a gate electrode stack comprising a bottom polysilicon portion and a top silicide portion are also known. The layer of silicide in such a gate electrode stack contributes to a decrease in the resistance of the gate. The decrease in resistance causes a decrease in the time propagation delay RC of the gate. Although a silicide top gate region may help decrease the resistance of the transistor, charge is still depleted in the vicinity of the interface formed between the bottom polysilicon gate and gate dielectric, thereby causing a smaller effective gate capacitance.
Another type of CMOS device that is available is one where the gate electrode includes at least a metal layer beneath a Si-containing, e.g., polysilicon, gate electrode. In such CMOS devices, the metal of the gate prevents depletion of charge through the gate. This prevents the decrease in effective thickness of the gate capacitance. Although metal-gated devices address the depletion problem mentioned above in regard to polysilicon gates, it is difficult to obtain nFET and pFET workfunctions using metal gated devices due to instability in threshold voltage. This is especially the case when high k dielectrics such as Hf-based dielectrics are used as the gate dielectric of metal gated devices.
In such technologies, high k metal dielectric stacks are needed to enable CMOS scaling to continue. The new generation of dielectric stacks offers the potential to achieve electrically thinner dielectrics with low gate leakage. In order to design metal gated high k devices using conventional methodologies, the gate electrode stacks should have the same workfunction as the polysilicon gated devices. Thus, two gate electrode stacks are needed, one for the nFET device and another for the pFET device.
Although a considerable amount of effort and progress has been made to find p-type and n-type gate electrode stacks, it is unlikely that suitable options will be found for both simultaneously. It is more likely that one acceptable gate electrode stack (either n or p) would be found first.
Circuit performance would improve significantly even if one of the devices included a gate stack with a high k dielectric and a band edge workfunction. Therefore, the need exists for a semiconductor structure where one device includes a gate electrode stack that includes a Si-containing electrode and an overlying first metal and the other device includes a gate electrode stack that includes the first metal without, the underlying Si-containing electrode.